13 March to 24 April 2010

Introduction

Using Field Programmable Gate Arrays (FPGAs) as processing engines is a growing and fertile application field; FPGAs perform particularly well when used to accelerate computationally intensive applications. MCS being the centre of excellence of Telecommunications has arranged a course on FPGA based chip design. The course is being organized by Maj. Dr. Abdul Ghafoor and will be presented by Engr. Fayaz Hussain Gillani who is an expert on FPGA Based Chip Design and affiliated with And Or Logic Pvt. Ltd. The main goal of the course is to increase understanding and knowledge of FPGAs and encourage growth and development in the field.

Description

This course covers design simulation, verification / testing and synthesis / implementation of FPGA based digital systems using the standard Verilog hardware description language and synthesis tools. It also covers Digital Signal Processing (DSP) implementation on FPGAs and real time debugging with Xilinx ChipScope Pro tools. Computer Aided Design (CAD) tools are used for experiments. We will use the ISE™ software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture and learn the best design practices from the pros and understand the subtleties of the Xilinx design flow. This course covers ISE 8.2i features, such as the Architecture Wizard and the Floor plan Editor.

Program:

The course has been divided in number of short duration lectures to increase the effectiveness of theoretical information followed by practical lab work. A week’s break provides participants time to practice what they have learned and come prepared in next session with their feedback as well as their queries.

Course Dates:    13th Mar 2010, Saturday

20th Mar 2010, Saturday

26th Mar 2010, Friday

10th Apr 2010, Saturday

24th Apr 2010, Saturday

 

Timing:                1000 to 1200 hrs

Venue:                 ECR & Comp Lab - I - MCS, Rawalpindi

Workshop Date:  13 March - 24 April, 2010

Registration Fee:      

• PG Students / Faculty / Professionals / Others        

• UG Students                 

Rs-2,000

Rs-1,000

Registration Deadline: March 10, 2010

Important Notes:

Please bring your Original ID cards and Student ID cards (if applicable). Please be 30 minutes prior to the start of Seminar. Further details can be reached to the following contact persons.

Registration by cash payment or through cheques/ bank drafts. Make cheques payable in Pakistani Rupees to Telecomm Society M.C.S, Habib Bank Ltd Lalkurti. All attendees are requested to complete a registration form and send it by post mail or email along the payment receipt, latest by 12th Mar 2010 to:

Postal Address:     Dr. Abdul Ghafoor

Electrical Engineering Department

Military College of Signals

Humayun Road, Lalkurti,

Rawalpindi.

For queries and Confirmation, please mail to: fpgaworkshop@mcs.edu.pk

(1)   Dr Abdul Ghafoor                      (2)  Engr. Intisar Rizwan - i - Haque
       EE Dept, MCS, NUST                    EE Dept, MCS, NUST
       +92-51-561523345                         +92-334-5064535
       abdulghafoor.mcs@gmail.com        intisarrizwan@gmail.com
       abdulghafoor-mcs@nust.edu.pk      intisar@mcs.edu.pk